In a receiver section of wireless or wire communication system, a low noise amplifier makes a first circuit block which has a gain first, and therefore the noise figure (NF) of the low noise amplifier is added into the noise figure of the system as it is. In the receiver section, the conjugate matching of the antenna and low noise amplifier is performed in order to attain a signal power as large as possible. Specifically, the low noise amplifier is designed so that it has a resistance component of input impedance of 50 ohms.
Non-patent Document 1, which is to be specified later, introduces various architectures of low noise amplifiers. It is stated that with the resistive termination technology of the first architecture, a low noise amplifier has a poor noise characteristic owing to a detrimental effect of the real resistance of an input port. As to the 1/gm termination method of the second architecture (also referred to as the common gate termination method), it is stated that bipolar transistors are more suitable to achieve a low noise figure performance than complementary metal oxide semiconductors (CMOS). In regard to the shunt series feedback of the third architecture, it is stated that electric power consumption is increased in comparison to other methods in case that the coordinative noise performance is achieved. With the inductive source degeneration method of the fourth architecture, a real part of the input impedance is created by using an inductor for a source terminal. According to the document it is stated that this method is often used together with a cascode transistor, and has been used widely in designing a low noise amplifier because of its good noise performance and reverse isolation, and a high gain being achievable.
Also, Non-patent Document 1 describes an inductive source degeneration low noise amplifier using both the cascode transistor and shunt feedback, and a fully differential low noise amplifier as an extension of the inductive source degeneration low noise amplifier. Further, Non-patent Document 1 contains the description that an N-type additional MOS transistor is connected in parallel with the cascode transistor for the purpose of materializing a variable gain of a low noise amplifier.
In addition, Non-patent Document 2, which is to be specified later, describes a inductive degeneration common source low noise amplifier used for an ultra wideband (UWB) system of 3.1 to 10.6 GHz. A cascode transistor is also used for the low noise amplifier. To enhance the design flexibility, an inductor is connected in series with the gate of a common source transistor, and a capacitance is connected between the gate and source of the transistor. In the low noise amplifier, a doubly terminated three-section passband Chebyshev filter is used to resonate an inductive part of the input impedance over a whole bandwidth extending between 3.1 and 10.6 GHz. As a result, a total of five inductors are used in the low noise amplifier described in Non-patent Document 2.
Further, Non-patent Document 2 describes that the source of the common source transistor is connected to a substrate (bulk) for the purpose of enhancing the performance of the low noise amplifier. The common source transistor is an N channel MOS transistor, which is constructed by a triple well device. The triple well device uses a p-type substrate, an n-type well formed in the p-type substrate, and p-type well formed in the n-type well.
Non-patent Document 3, which is to be specified later, describes a low noise amplifier used for an ultra wideband (UWB) system of 3.1 to 10.6 GHz; the low noise amplifier uses two inductors, which is a relatively small figure. The low noise amplifier uses a heterojunction bipolar transistor of SiGe. The wideband input matching of this low noise amplifier is materialized in a common base input stage which enables a good noise matching impedance in an UWB frequency range up to 10.6 GHz. The common base input stage is identical in principle with the 1/gm termination method (common gate termination method) described in Non-patent Document 1. The emitter of a common base transistor is supplied with an RF input signal through a coupling capacitance, and the emitter of the common base transistor is connected to a ground voltage through an emitter biasing inductor, which is the first inductor, and a CR parallel circuit. A base bias voltage is applied to the base of the common base transistor through a base termination inductor, which is the second inductor. The rise in the base termination inductor increases the gain of the common base input stage until a resonance frequency decided by the product of the base termination inductance and the base input capacitance of the common base transistor. It is stated that the increase in the gain reduces the equivalent noise voltage, whereby the noise figure is improved. The gain stage making the second stage of this low noise amplifier is composed of a variable gain resistive feedback amplifier including a common emitter transistor, a collector load resistance, an emitter follower for feedback, and a feedback resistance. Also, the low noise amplifier includes an output emitter follower of the third stage.
On the other hand, Patent Document 1, which is to be specified later, describes a wideband amplifier having a transistor for amplifier, and a switch transistor connected to a base bias circuit of the transistor for amplifier, which is supplied with an OF/OFF switching voltage. When the switch transistor is in OFF state, the base bias voltage is higher, the collector current of the transistor for amplifier is larger, the negative feedback from the emitter toward the base is larger, and therefore the distortion is made smaller, which is suitable to amplify a strong electric field signal. When the switch transistor is in ON state, the base bias voltage is lower, the collector current of the transistor for amplifier becomes lower, the negative feedback from the emitter toward the base is smaller, and the gain is increased, and the noise figure is improved, which is suitable to amplify signals of weak and middle electric fields.
Now, the references cited herein are as follows.
Patent Document 1: JP-A-2005-348101.
Non-patent Document 1: Chetty Garuda et al, “A 3-5 GHz Fully Differential CMOS LNA with Dual-gain mode for Wireless UWB Application”, 2005, 48th Midwest Symposium on Circuits and Systems, Vol. 1, pp. 790-793, 7-10, Aug. 2005.
Non-patent Document 2: Andrea Bevilacqua et al, “An Ultrawideband CMOS Low-Noise Amplifier for 3.1-10.6-GHz Wireless Receivers”, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004, pp. 2259-2268.
Non-patent Document 3: Nobuhiro Shiramizu et al, “A 3-10 GHz Bandwidth Low-Noise and Low-Power Amplifier for Full-Band UWB Communications in 0.25-μm SiGe BiCMOS Technology”, 2005 IEEE Radio Frequency Integrated Circuits Symposium, pp. 39-42.